
10
FN4343.5
August 20, 2009
16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats
with Flicker Filtering
When the 16-bit YCbCr, 16-bit RGB, or 24-bit RGB data
format is selected and flicker filtering is enabled, pixel and
overlay data is latched on every rising edge of CLK2. The
pixel and overlay input timing is shown in Figures 9-11.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
FIGURE 9. PIXEL AND OVERLAY INPUT TIMING - 16-BIT YCBCR WITH FLICKER FILTERING
FIGURE 10. PIXEL AND OVERLAY INPUT TIMING - 16-BIT RGB WITH FLICKER FILTERING
FIGURE 11. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH FLICKER FILTERING
CLK2
BLANK
(INPUT)
BLANK
(OUTPUT)
Y 0
Y 1
Y 2Y 3Y 4Y 5
P8-P15
Cb 0Cr 0
Cb 2Cr 2
Cb 4
Cr 4
P0-P7
PIXEL 0
PIXEL 1
PIXEL 2
PIXEL 3
PIXEL 4
PIXEL 5
OL0-OL2,
M1, M0
Y N
Cr N-1
PIXEL N
CLK2
BLANK
(INPUT)
BLANK
(OUTPUT)
P0-P15
PIXEL 0
PIXEL 1
PIXEL 2
PIXEL 3
PIXEL 4
PIXEL 5
OL0-OL2,
M1, M0
PIXEL N
RGB 0
RGB 1
RGB 2
RGB 3
RGB 4
RGB 5
RGB N
CLK2
BLANK
(INPUT)
BLANK
(OUTPUT)
RGB 0RGB 1RGB 2RGB 3RGB 4RGB 5
P0-P23
RGB N
HMP8154, HMP8156A